1. Field of the Invention
The present invention relates to a semiconductor device and a data transfer method. More particularly, the present invention relates to a semiconductor device and data transfer method for performing DMA transfer.
2. Description of the Related Art
In an information terminal such as a digital camera or a cellular phone, a memory card incorporating a nonvolatile memory such as a flash memory is used as a recording medium of data.
The memory card is controlled by a card controller incorporated in a system Large Scale Integrated circuit (LSI) mounted on an information terminal.
In a case of transferring data to the memory card, there is known a Program I/O transfer (PIO) where a Central Processing Unit (CPU) within the system LSI accesses a card as an Input/Output (I/O) device through the card controller. In the case of performing the data transfer by the PIO, the CPU is occupied during the data transfer. Therefore, when transferring large data, system throughputs are reduced.
On the other hand, there is known a Direct Memory Access (DMA) transfer where data transfer is directly performed between an I/O device and a memory without using a CPU. By using the DMA transfer, large data can be transferred without disturbing processing of the CPU.
In order to perform the DMA transfer, the I/O device must generally have a DMA interface. The reason is that the DMA interface is required to interpret a signal such as a DMA transfer request signal or DMA transfer permission signal transmitted to and received from a DMA controller. In the meanwhile, a DMA transfer method capable of the DMA transfer without the DMA interface is disclosed, for example, in Japanese Unexamined Patent Application Publication No. Hei 8-194660.
FIG. 12 shows a configuration of a conventional semiconductor device for performing DMA transfer to and from an I/O device having no DMA interface.
A semiconductor device 500 has a CPU 501, a memory 502, a DMA controller 503, a switching section 504 and a request generating section 505. In the device 500, these are connected to a system bus 506. FIG. 12 shows the following case. A memory card 507a is used as the I/O device. The semiconductor device 500 incorporates a card controller 507. The card controller 507 is connected to the system bus 506 through the switching section 504. The CPU 501 and the DMA controller 503 are masters of the system bus 506, and the card controller 507 is a slave thereof.
Herein, the switching section 504 switches whether to connect between the CPU 501 and the card controller 507, or to connect between the DMA controller 503 and the card controller 507. Specifically, when the CPU 501 is a master, the section 504 connects the CPU 501 to the card controller 507 so as to transmit to the card controller 507 a control signal such as an address signal or a chip select signal, or data.
On the other hand, when the DMA controller 503 is a master, the switching section 504 cuts off a control signal from the CPU 501 and transmits to the card controller 507 a chip select signal newly generated from a DMA transfer permission signal inputted from the DMA controller 503, a fixed address signal (I/O port address), and data of the memory 502 connected to the system bus 506.
The request generating section 505 transmits a DMA transfer request signal to the DMA controller 503 at a constant interval set in an interval setting section 508.
FIG. 13 is a timing chart showing a signal state during data transfer of the conventional semiconductor device.
This timing chart shows a bus clock transmitted through the system bus 506, a chip select signal/CSa outputted by the CPU 501, a DMA transfer permission signal issued to the switching section 504 by the DMA controller 503, a DMA transfer ready signal and DMA transfer request signal transmitted to the DMA controller 503 by the request generating section 505, a chip select signal/CSb inputted to the card controller 507, and data of the system bus 506.
FIG. 13 shows a case where an access cycle of the card controller 507 is three clock cycles.
During PIO transfer, the chip select signal/CSa issued by the CPU 501 is used as the chip select signal/CSb of the card controller 507. In other words, the switching section 504 transmits a control signal from the CPU 501 to the card controller 507. Thus, data (valid in FIG. 13) is transferred by PIO between the memory 502 and the card controller 507 under the control of the CPU 501.
Successively, the DMA transfer request signal generated by the request generating section 505 is asserted (in FIG. 13, the signal goes to “H (High)”). At this time, an idle cycle is inserted until the DMA transfer permission signal generated by the DMA controller 503 is asserted to permit the transfer.
During the DMA transfer, the switching section 504 generates the chip select signal/CSb of the card controller 507 based on the DMA transfer permission signal issued by the DMA controller 503. In other words, the switching section 504 transmits a control signal from the DMA controller 503 to the card controller 507. Thus, data is transferred by DMA between the memory 502 and the card controller 507 under the control of the DMA controller 503.
Also during the DMA transfer, the chip select signal/CSb inputted to the card controller 507 must be generated such that an access cycle in the card controller 507 is the same as that in the PIO transfer. When the chip select signal/CSb is generated based on only the DMA transfer permission signal, the DMA transfer permission signal issued by the DMA controller 503 must be made active during the access cycle of the card controller 507 (three clock cycles herein). For example, when the request generating section 505 makes the DMA transfer ready signal “L (Low)” and transmits to the DMA controller 503 the information that the signal is in a state of transfer ready, the DMA transfer permission signal can be made active by necessary cycles. When the DMA transfer ready signal is unable to be used, the switching section 504 makes “L” the chip select signal/CSb inputted to the card controller 507 and starts asserting the chip select signal/CSb in response to a rising edge of the DMA transfer permission signal. When making the chip select signal/CSb active and “H” by the access cycles, the section 504 negates the signal.
When detecting a rising edge of the DMA transfer permission signal, the switching section 504 negates the DMA transfer request signal issued from the request generating section 505 to the DMA controller 503. The interval setting section 508 can set the number of cycles where the DMA transfer request signal is negated and then asserted. FIG. 13 shows a case of setting three clock cycles equivalent to the access cycle.
FIG. 14 is a flowchart showing operations during the DMA transfer to the memory card through the conventional semiconductor device.
First, setting of the transfer mode or issuance of the transfer command is performed from the CPU 501 to the card controller 507 through the switching section 504 (step S50).
Next, the DMA controller 503 is started to initiate the DMA transfer (step S51). When the DMA transfer is initiated, the request generating section 505 continues to issue at regular intervals a transfer request to the DMA controller 503 based on a value set in the interval setting section 508.
During the data transfer, whether data is normally transferred must be checked every time a constant amount of data is transferred (hereinafter referred to as a status check). It is determined whether the transfer of a transfer unit is completed (step S52). When the transfer of the transfer unit is completed, this status check is performed (step S53). The status check is performed by accessing the card controller 507 or the memory card 507a from the CPU 501 to read a status.
After the status check is performed, it is determined whether the data transfer is completed (step S54). When data desired to be transferred still remains, the operation returns to the processing in step S51. The DMA controller 503 is restarted to again initiate the transfer. Thereafter, the processings in steps S51 to S54 are repeated until transfer of the whole data is completed.
According to such a conventional semiconductor device 500, the DMA transfer can be performed using an I/O device without the DMA interface.
However, in the conventional semiconductor device 500 as shown in FIG. 12, while the request generating section 505 issues the DMA transfer request, the switching section 504 transmits to the card controller 507 a control signal from the DMA controller 503. Therefore, the CPU 501 is unable to access the card controller 507 or the memory card 507a. In order to access from the CPU 501, the DMA transfer must be completed. Accordingly, in the conventional semiconductor device 500, the DMA controller 503 must be restarted in each status check as shown in FIG. 14 and as a result, transfer processing suffering from high overhead is performed.